The invention relates to CMOS devices. In particular, the present invention relates to deep submicron CMOS devices and methods for making at least a portion of such devices.
As semiconductor device features shrink in size and feature density increases, problems arise concerning the formation of the semiconductor devices. Often, feature requirements conflict with competing concerns involved in making the device features smaller and more densely packed in a given surface area.
The present invention provides a method for forming source/drain extensions with gate overlap. The method includes forming an oxide layer on a gate structure on a semiconductor substrate. Sidewall spacer regions are formed on the sides of the gate structure. Spacer regions are formed on the sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided along with portions of source/drain extension regions in the semiconductor substrate adjacent the gate structure.
Additionally, the present invention concerns a method of forming a semiconductor device structure. A gate oxide region is formed on a semiconductor substrate. A gate structure is formed on the gate oxide region. An oxide layer is formed on the semiconductor substrate and gate structure. Source and drain extension regions are implanted in the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Deep source/drain regions are implanted in the semiconductor substrate. Second spacer regions are formed on sides of the sidewall spacer regions. The oxide layer on the gate structure and on the sides of the gate structure in the vicinity of the top of the gate structure is removed. The gate structure and the sidewall spacer regions are silicided in the vicinity of the top of the gate structure and the sidewall spacer regions. Portions of the source/drain extension regions not covered by the sidewall spacer regions or the spacer regions are also silicided.
The present invention also includes a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate and a gate oxide region on portions of the semiconductor substrate. A gate structure is arranged on the gate oxide region. A portion of the gate structure in the vicinity of a top of the gate oxide region is silicided. First, sidewall spacer regions are arranged on sides of the gate structure. A portion of the sidewall spacer region in the vicinity of the top of the sidewall spacer regions is silicided. Second spacer regions are arranged on the sides of the sidewall spacer regions. An oxide layer is arranged between the semiconductor substrate and the sidewall spacer regions and the second spacer regions. Source/drain extension regions in the substrate underlie the sidewall spacer regions and the second spacer regions. Silicided source/drain extension regions are arranged in the substrate adjacent the source/drain extension regions in the substrate underlying the sidewall spacer regions and the second spacer regions. Source/drain regions underlie the source/drain extension regions and the silicided source/drain extension regions.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.